(1) Field of the Invention
This invention relates to a solid state imaging device, such as charge coupled device (CCD) imager, performing electrical shuttering on application of a pulse voltage to a substrate.
(2) Description of the Prior Art
In some of the solid state imaging devices, the output circuit has its source follower constituted by MOS transistors.
FIG. 5 shows the diagrammatic cross-section of the output circuit of the solid state imaging device. Briefly, a p-type well region 52 is formed on an n-type silicon substrate 51 fed with a substrate voltage V.sub.sub. On the surface of the p-type well region 52, there are formed a channel stop region 53, a source drain region 54 fed with a ground voltage V.sub.ss, a source drain region 55 for taking out an output voltage V.sub.OUT, and a source drain region 56 fed with a power source voltage V.sub.dd. Gate electrodes 57 and 58 are formed on channel-forming regions 59 and 60 between the adjacent source drain regions 54 to 56. Thus the source drain regions 54, 55 and the gate electrode 57 fed with a constant voltage V.sub.GG make up a load transistor while the source drain regions 55, 56 and the gate electrode 58 fed with an input voltage V.sub.in make up a driving MOS which is a field effect transistor. The p-type well region 52 has the junction depth of ca. 10 .mu.m and the surface impurity concentration of 1.times.10.sup.15 to 10.sup.16 cm.sup.-2.
In the above described solid state imaging device, there exist parasitic capacitance between each of the source drain regions 54 to 56 and the well region 52 or between the well region 52 and the substrate 51. There are also holes h in deeper portions of the p-type well region, as shown in FIG. 6. The region of these holes h present a larger resistance because the impurity concentration and the hole mobility are both low.
FIG. 7 shows an equivalent circuit of the output circuit of the solid state imaging device. By the resistance component of the holes h, resistances r.sub.11 to r.sub.16 are formed equivalently in the well region 52, whereas there are parasitic capacitances C.sub.11 to C.sub.15 between the substrate and the well and parasitic capacitances C.sub.21 to C.sub.25 between the well region and each electrode.
When electronical shuttering is performed with the use of the well region where there are the parasitic capacitances C.sub.11 to C.sub.15 and C.sub.21 to C.sub.25 and resistance r.sub.11 to r.sub.16 under application of a pulse voltage to the substrate, the pulse response waveform becomes blunt due to these capacitances and resistances. More specifically, electronic shuttering is usually performed by sweeping out useless electrical charges from the pixels to the substrate during the horizontal or vertical blanking periods, depending on the shuttering speed. Should the time constants defined by the parasitic capacitances C.sub.11 to C.sub.15 and C.sub.21 to C.sub.25 and by the resistances r.sub.11 to r.sub.16 exceed the horizontal (H) blanking period, the pulse voltage affects the output circuit to give rise to gain change or level fluctuations at the driving MOS field effect transistor to affect the produced image.